In dual job FLASH memory devices, in which it is possible to read data from a partition and modify data (programming or erasing) in another partition at the same time, an important problem to be addressed is that of minimizing or reducing the effects of disturbances generated by a data modification operation on an eventually simultaneous read operation, and vice-versa. These disturbances are mainly due to current absorption injection peaks from common supply nodes (Vdd, Gnd, boosted voltages).
The problem is often circumvented by separating, where possible, the supply lines of the read circuits from those of the program/erase circuits. However, in certain circuits this design is not applicable. An important example is the turning on and off of banks of sense amplifiers of the various partitions.
Indeed, to reach a good matching between read and verify operations, the verifications of the correct execution of modifications (program or erase) of data stored in a certain partition are carried out through the same sense amplifiers that are used for reading data from the partition. This is to eliminate the error due to possible differences among single sense amplifiers. Therefore, each memory partition has its own bank of sense amplifiers that perform both read and verify operations.
The banks of sense amplifiers are powered through the same supply lines, in particular, the same ground lines, as shown in FIG. 1. Generally, critical read operations, such as page mode or burst mode read operations, are accomplished with a high read in parallel. Moreover, for achieving the required access time, the power consumption of sense amplifiers is relatively large, and thus they cannot be kept constantly powered. Therefore, a request for a read or verify operation implies turning on the bank of sense amplifiers and turning it off at the end of the read or verify operation.
For illustration purposes, let us refer to an architecture in which each bank comprises 128 sense amplifiers and suppose that two operations are in progress. That is, a read operation is in progress in a partition and the program algorithm is starting a verify routine in another partition, as shown in FIG. 2.
Turning on the bank of sense amplifiers of a partition causes a current peak toward ground of several mA that determines an increase of the potential of the ground node conductor to which the NMOS transistors of the sense amplifier are connected. This transitory effect constitutes a disturbance that may cause an evaluation error if the amplifiers of the partition being verified are turned on in the critical phase of discrimination of logic values. The problem is even more critical in multilevel memory devices in which the discrimination margins between the threshold voltage distributions are reduced.
According of a common embodiment depicted in FIG. 3, each sense amplifier is composed of a differential amplifier that compares a reference current with that of the addressed cells. In particular, the precharge voltage of the selected bitline is obtained by a voltage VRIF that is locally generated and is referred to ground. An instantaneous fluctuation of the potential of the ground node Gnd determines a consequential variation of the reference voltage (coupled to the non-inverting input (+) of the differential amplifier) that on its turn on generates a disturbance current that is summed to that of the cell, thus potentially affecting discrimination. Similarly, even turning off a bank of sense amplifiers induces a significant disturbance on the ground potential.
The above discussed example refers to a disturbance on the ground node potential, but the same problem is present on all supply nodes. This kind of problem is usually tackled by designing with great care the ground distribution lines to the sense amplifiers to minimize resistive paths. This approach, even if useful, may be insufficient to cope with the effects of absorption peaks of large amplitude. This may be due to the simultaneous turning on of a large number of circuits, such as with banks of sense amplifiers, for instance.
It is observed that what may fault a read operation is not a fluctuation of the absolute value of the voltage referred to the ground potential, but its variation during the critical phase of discrimination of the logic value.